It is well known to those skilled in the art that the goal in the design and manufacture of RFID tags is to provide low-cost miniature components which, when assembled, will be susceptible of incorporation in a wide variety of applications where miniaturization and low cost are requisite.
Typical of prior art attempts at miniaturization and low cost are the arrangement of the components of the circuit in a uniform plane with the conductors incorporated in the circuit disposed in said plane.
However, the conductive securement of the IC circuit to the antenna continues to pose problems in that it increases the thickness of the assemblage and prevents the utilization of such combinations in many applications such as miniaturized PFID tags.
Consequently, in ultra-miniature circuits, for example RFID tags, miniaturizing circuit dimensions and decreasing production costs are ongoing objectives. Recent patents teach methods of implementing this miniaturization with respect to attachment of the integrated circuits to the antenna by the simplest, lowest profile and most economical means conceived of at the time (e.g., Marsh U.S. Pat. No. 5,566,441 and Moskovitz U.S. Pat. No. 5,528,222).